The present invention relates to vertical type power MOSFETs (metal-oxide semiconductor field effect transistors) designed to prevent, or reduce the risk of, latch-up.
The vertical MOSFETs are used as power switching elements. However, it is difficult to increase a withstand voltage of a standard vertical MOSFET without increasing its on resistance. Recently, a new vertical MOSFET has been developed and appeared in the market. The new device is designed to overcome the disadvantage of the standard vertical MOSFET by utilizing conductivity modulation. This new device is known as a conductivity modulated MOSFET or a bipolar mode MOSFET.
FIGS. 6 and 7 show one conventional example of the conductivity modulated MOSFETs (disclosed in IEEE, IEDM 83, pages 79-82).
The semiconductor device of FIG. 6 is composed of an epitaxial substrate 1 which consists of a P.sup.+ -type Si substrate 2 serving as a drain region, and an n-type base layer 3 formed on the P.sup.+ substrate 2 by epitaxial growth. The impurity concentration, and thickness of the epitaxial layer 3 are chosen in accordance with the required withstand voltage.
In a principal surface of the epitaxial substrate 1, there are formed a p-type semiconductor channel region 4, a p.sup.+ -type semiconductor base region 5, and an n.sup.+ -type semiconductor source region 6 straddling the channel region 4 and the base region 5.
The vertical MOSFET of FIG. 6 is the n-channel type. Therefore, the n epitaxial layer 3 serves, in effect, as a drain region. In the conductivity modulation type of MOSFETs, however, this epitaxial layer 3 is called an n-type base layer because of its operation.
A gate electrode 8 is formed above the channel region 4 lying between the n.sup.+ source region 6 and the n base epitaxial layer 3, and separated from the channel region 4 by a gate insulating oxide layer 7.
The device of FIG. 6 further includes a PSG intermediate insulating layer 9, a source electrode 11 and a drain electrode 12. The source electrode 11 is connected to the channel region 4 through the n.sup.+ source region 6 and the P.sup.+ base region 5. The drain electrode 12 is formed on the bottom of the p.sup.+ substrate 2.
Such a conductivity modulated device has an advantage that it can possess high withstand voltage and low on-resistance simultaneously. In the standard vertical MOSFET in which the p.sup.+ drain region 2 is replaced by an n.sup.+ -type region, the resistance of the n base epitaxial layer 3 increases in proportion to the withstand voltage raised to the power of 2.7, so that it is difficult to attain a sufficiently low on resistance when the withstand voltage is 400 V or more.
In the device of FIG. 6, there is formed a parasitic pnpn thyristor structure composed of a parasitic pnp transistor Q.sub.1 and a parasitic npn transistor Q.sub.2 as shown in FIG. 6. Both transistors Q.sub.1 and Q.sub.2 are connected as shown in an equivalent circuit of FIG. 7. A resistance Rb shown in FIG. 7 is a base resistance of the transistor Q.sub.2, which is formed in the p.sup.+ base region 5 and the channel region 4.
When a predetermined positive voltage is applied to the drain electrode 12, and a gate-source voltage equal to or greater than a threshold voltage is applied between the gate electrode 8 and the source region 6, then a surface layer of the channel region 4 immediately below the gate electrode 8 becomes conductive. Therefore, electrons flow from the n.sup.+ source region 6 through the channel region 4 into the n base layer 3. On the other hand, a large number of holes are injected from the p.sup.+ drain region 2 into the n base layer 3.
A part of the holes injected into the n base layer 3 recombine with the electrons coming from the channel region 4, and a part of the holes flow into the p.sup.+ base region 5 and the channel region 4, and reach the source electrode 11. Nevertheless, a large number of carriers are stored in the n base layer 3. As a result, the conductivity of the n base layer 3 is modulated, or increased, and the on resistance of the device is dramatically reduced.
The conductivity modulated MOSFET is very advantageous in that its on resistance is very low, and therefore it can handle higher current level. However, this new device has a problem of latch up. If the output current of the device is increased in such a extent as to cause a voltage drop developed by the base resistance Rb to exceed a base threshold voltage (0.6 V, for example), then the transistor Q.sub.2 is turned on, so that the transistor Q.sub.2 increases its collector current, that is, a base current of the other transistor Q.sub.1. As a result, latch-up is caused by formation of a positive feedback loop in which the base current of the transistor Q.sub.2 is increased by increase of the collector current Ic.sub.1 of the transistor Q.sub.1. Latch-up is very harmful since it is necessary to cut off the power supply in order to restore the thyristor once switched to latch-up, to the original state.
The condition for triggering latch-up is expressed as: EQU Ic.sub.1 .multidot.Rb.gtoreq.0.6 (V)
Therefore, in order to prevent latch up, it is important to minimize the collector current Ic.sub.1 of the transistor Q.sub.1 and/or the base resistance Rb.
FIG. 8 shows another conventional example of the conductivity modulated vertical MOSFETs (disclosed in H. Ohashi et al. "Basic Characteristics of Bipolar-Mode MOSFET", Denshi Tsushin Gakkai Gijutsu Hokoku, SSD85-22, pages 1-7, 1985). In the device of FIG. 8, there are additionally provided an n.sup.+ buffer layer 17 formed by epitaxial growth between the p.sup.+ drain substrate region 2 and the n base layer 3, and one or more bypass regions 18 formed in the channel region 4.
The n.sup.+ buffer layer 17 is intended to reduce the collector current Ic.sub.1 of the transistor Q.sub.1 by restricting the efficiency of injecting holes from the p.sup.+ drain region 2 into the n base layer 3. The bypass regions 18 are intended to obtain an effect equivalent to reduction of the base resistance Rb by providing a low resistance bypass for the hole current
However, the conductivity modulated MOSFET structure of FIG. 8 is disadvantageous in that its on resistance is increased by the n.sup.+ buffer layer 17 and the bypass region 18, and that the fabrication of the device is complicated by a double epitaxial growth process for forming the n.sup.+ buffer layer 17.